Alliance Memory Low-Power DDR2 SDRAM

Alliance Memory Low-Power DDR2 SDRAM are high-speed CMOS and dynamic-access memory internally configured as an 8-bank device. These DDR2 SDRAM feature 4-bit pre-fetch DDR architecture, programmable READ and WRITE latencies, auto Temperature Compensated Self Refresh (TCSR), and clock stop capability. The DDR2 SDRAM reduces the number of input pins in the system by using a double data rate architecture on the Command/Address (CA) bus. This CA bus transmits address, command, and bank information. These DDR2 SDRAM can achieve high-speed operation by using a double data rate architecture on the DQ (bidirectional/differential data bus) pins.


  • 400MHz maximum clock frequency range
  • 4-bit pre-fetch DDR architecture
  • Low voltage power supply
  • Auto TCSR
  • Partial Array Self Refresh (PASR) power-saving mode
  • Deep Power Down (DPD) mode
  • Driver Strength (DS) control
  • Eight internal banks for concurrent operation
  • Multiplexed, double data rate, and command/address inputs
  • Bidirectional/differential data strobe per byte of data
  • DM masks write data at the rising and falling edge of the data strobe
  • Programmable READ and WRITE latencies (RL/WL)
  • 4, 8, or 16 programmable burst lengths
  • Supports auto and self refresh
  • Supports all bank auto refresh and per bank auto refresh
  • Clock stop capability
  • -40°C to 85°C operating temperature range

DDR2 SDRAM Block Diagram

Block Diagram - Alliance Memory Low-Power DDR2 SDRAM
Published: 2018-06-28 | Updated: 2022-11-07