Analog Devices Inc. AD9082 Mixed Signal Front-End (MxFE®)

Analog Devices Inc. AD9082 Mixed-Signal Front-End (MxFE®) is highly integrated with a 16-bit, 12GSPS maximum sample rate digital-to-analog converter (DAC) core, and 12-bit, 6GSPS rate, RF analog-to-digital converter (ADC) core. The AD9082 supports four transmitter channels and two receiver channels, making it well suited for applications requiring both wideband ADCs and DACs to process signal(s) having wide instant bandwidth.

The ADI AD9082 features a 16 lane, 24.75Gbps/lane JESD204C or 15.5Gbps/lane JESD204B data transceiver port, an on-chip clock multiplier, and a digital signal processing (DSP) capability. These features are targeted at either wideband or multiband, direct to RF applications. Additionally, the AD9082 MxFE offers a bypass mode that allows the ADC or DAC cores' full bandwidth capability to bypass the DSP datapaths.

The AD9082 MxFE provides a low latency loopback and frequency hopping mode designed for phased array radar systems and electronic warfare applications.


  • Flexible reconfigurable common platform design
    • 4 DACs and 2 ADCs (4D2A)
    • Supports single, dual, and quad-band
    • Maximum DAC/ADC sample rate up to 12GSPS/6GSPS
      • DAC to ADC sample rate ratios of 1, 2, 3, and 4
      • ADC and DAC datapath bypass option
      • Analog bandwidth to 8GHz
      • 7mA to 40mA Full-scale output current range, ac coupling
    • On-chip PLL with multichip synchronization
      • External RFCLK input option
  • ADC AC performance at 6GSPS
    • 1.475Vp-p Full-scale input voltage
    • 4.4dBm Full-scale sine wave input power
    • -153 dBFS/Hz Noise density
    • 25.3dB Noise figure
    • -65.2dBFS at 2.7GHz HD2
    • -70.8dBFS at 2.7GHz HD3
    • -68.5dBFS at 2.7GHz Worst other (excluding HD2 and HD3)
  • DAC ac performance at 3.7GHz output
    • -78.9dBc 2-tone IMD3 (-7dBFS per tone)
    • -155.1dBc/Hz NSD, single-tone, fDAC = 12GSPS
    • -70dB SFDR, single-tone, fDAC = 12GSPS
  • Programable delay per data path
  • Receive AGC support
    • Fast detect with low latency for fast AGC control
    • Signal monitor for slow AGC control
    • Dedicated AGC support pins
  • Transmit DPD support
    • Fine DUC channel gain control and delay adjust
    • Coarse DDC delay adjust for DPD observation path
  • Versatile digital features
    • Supports real or complex digital data (8-, 12-, 16-, or 24-bit)
    • Selectable interpolation and decimation filters
    • Configurable DDC and DUC
      • 8 fine complex DUCs and 4 coarse complex DUCs
      • 8 fine complex DDCs and 4 coarse complex DDCs
      • 48-bit NCO per DUC/DDC
      • Option to bypass fine and coarse DUC/DDC
  • Programmable 192-tap PFIR filter for receive equalization
    • Supports 4 different profile settings loaded via GPIO
  • Auxiliary features
    • Fast frequency hopping
    • Direct digital synthesis (DDS)
    • Low latency digital loopback mode (ADC to DAC)
    • ADC clock driver with selectable divide ratios
    • Power amplifier downstream protection circuitry
    • On-chip temperature monitoring unit
    • Flexible GPIOx pins
    • TDD power savings option
  • SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75Gbps
    • 8 lanes per DACs and ADCs
    • JESD204B compatible with the maximum 15.5Gbps lane rate
    • JESD204C compatible with the maximum 24.75Gbps lane rate
    • Sample and bit repeat mode for lane rate matching
  • 15mm × 15mm, 324-ball BGA with 0.8mm pitch
  • 11.45W typical Total power consumption


  • Wireless communications infrastructure
  • Microwave point-to-point, E-band and 5G mmWave
  • Broadband communications systems
  • DOCSIS 3.1 and 4.0 CMTS
  • Phased array radar and electronic warfare
  • Electronic test and measurement systems


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Block Diagram

Block Diagram - Analog Devices Inc. AD9082 Mixed Signal Front-End (MxFE®)
Published: 2020-08-24 | Updated: 2022-03-11