Analog Devices Inc. ADIN1300 10/100/1000 Gigabit Ethernet PHY

Analog Devices ADIN1300 10/100/1000 Gigabit Ethernet PHY is a low power single-port Gigabit Ethernet transceiver with industry-leading latency specifications primarily designed for industrial Ethernet applications. This design integrates an Energy Efficient Ethernet PHY core plus all the associated common analog circuitry, input and output clock buffering, the management interface and subsystem registers. It also includes the MAC interface and control logic to manage the reset and clock control and pin configuration.


  • 10BASE-Te/100BASE-TX/1000BASE-T IEEE® 802.3TM compliant MII, RMII and RGMII MAC interfaces
  • 1000BASE-T RGMII latency TX <68ns, RX <226ns
  • 100BASE-TX MII latency TX <52ns, RX <248ns
  • EMC Test Standards
    • IEC 61000-4-5 surge (±4kV)
    • IEC 61000-4-4 electrical fast transient (EFT) (±4kV)
    • IEC 61000-4-2 ESD (±6kV contact discharge)
    • IEC 61000-4-6 conducted immunity (10V)
    • EN55032 radiated emissions (CLASS A)
    • EN55032 conducted emissions (CLASS A)
  • Unmanaged configuration using multi-level pin strapping
  • Energy Efficient Ethernet (EEE) in accordance with IEEE 802.3az
  • Start of Frame Detection for IEEE 1588 Time Stamp Support
  • Enhanced Link Detection
  • Configurable LED
  • Crystal Oscillator/25MHz clock input (50MHz for RMII)
  • 25MHz/125MHz Synchronous clock output
  • Small Package and Wide Temperature Range
    • 40-lead (6mmx6mm) LFCSP
    • Specified for -40°C to +105°C ambient operation
  • Low Power Consumption
    • 330mW - 1000BASE-T
    • 140mW - 100BASE-TX
    • 3.3V/2.5V/1.8V MAC interface VDDIO supply
    • Integrated power supply monitoring and POR


  • Industrial automation
  • Process control
  • Factory automation
  • Robotics/Motion Control
  • Building automation
  • Test and Measurement
  • Industrial IoT


Functional Block Diagram

Block Diagram - Analog Devices Inc. ADIN1300 10/100/1000 Gigabit Ethernet PHY

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Published: 2019-10-04 | Updated: 2023-01-16